Regviz

Alif Semiconductor /AE722F80F55D5AS_CM55_HE_View /LPUART /UART_DET

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as UART_DET

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Alif Semiconductor/AE722F80F55D5AS_CM55_HE_View/LPUART/UART_DET#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DE_ASSERTION_TIME0DE_DE_ASSERTION_TIME

Description

Driver Output Enable Timing Register

Fields

DE_ASSERTION_TIME

Driver Enable Assertion Time This field controls the amount of time (in terms of number of SCLK periods) between the assertion of rising edge of DE signal to serial transmit enable. Any data in transmit buffer, will start on UART_TX signal after the transmit enable.
DE_DE_ASSERTION_TIME

Driver Enable Deassertion Time This field controls the amount of time (in terms of number of SCLK periods) between the end of the stop bit on the UART_TX signal to the falling edge of DE signal.

Links

()

Register License

THIS SOFTWARE IS PROVIDED “AS IS”. NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. ALIF SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data